Overview
These notes cover the SystemVerilog features that matter for verification work — from the logic type through the covergroup, with stops at randomization, inheritance, concurrent threads, and the Direct Programming Interface.
The material is organized into three parts. Each part ends with a 20-question exam to check understanding.
Reference sections
Verification guidelines, types, procedural flow
Bugs, plans, bench shape. The logic type. Packed arrays. Fixed and dynamic collections. Procedural statements and routines.
OOP, randomization, interfaces
Classes and inheritance. Constrained random generation. Coverage groups. Interfaces, modports, and clocking blocks.
Threads, mailboxes, assertions, DPI
Concurrent threads and synchronization. Mailboxes and semaphores. Assertions and SVA. The Direct Programming Interface.
How to use these notes
These aren't a replacement for the full language spec or textbooks. They're practitioner's notes — the things that come up in real verification work, explained the way a senior engineer would explain them at a whiteboard.
If you're already familiar with SystemVerilog, skim Part I for the idioms and jump to the exams. If you're newer, read the parts in order and take each exam before moving on.
Related
When you're ready to build a testbench, the UVM generator will scaffold a full project for you — agent, sequences, environment, scoreboard, tests — based on an interface you describe.